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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
January.2000 Ver. 4.0
Prepared by: Jae-Su, Ko
Ko1942@samsung.co.kr Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
KS0715 Specification Revision History Version Content CAP3P C3+, CAP2P C2+, CAP1P C1+ CAP3M C3-, CAP2M C2-, CAP1M C1Oscillator frequency FOSC (kHz) = 19 (Min.): 22.5 (Typ.): 26 (Max.) FCL (kHz) = 2.37 (Min.): 2.81 (Typ.): 3.25 (Max.) Temperature coefficient TEMPS = L: -0.0%/C -0.05%/C Absolute maximum ratings VLCD: +0.3 to +15.0 -0.3 to +17.0 Dynamic current consumption IDD1: 40A (Max.) IDD2: 75A (Typ.), 100A (Max.) Oscillator frequency (internal) 19: 22.5: 26 17: 22.5: 27 Oscillator frequency (external) 2.13: 2.81: 3.25 2.13: 2.81: 3.37 Change VDD Range : 2.4V to 5.5V 2.4V to 3.6V Date
1.0
2.0
3.0 3.1 4.0
Apr.1999 Jan.2000
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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION ..................................................................................................................................................1 FEATURES ..........................................................................................................................................................1 BLOCK DIAGRAM ...............................................................................................................................................3 PAD CONFIGURATION .......................................................................................................................................4 PAD CENTER COORDINATES............................................................................................................................5 PIN DESCRIPTION ..............................................................................................................................................7 POWER SUPPLY..........................................................................................................................................7 LCD DRIVER SUPPLY..................................................................................................................................7 SYSTEM CONTROL .....................................................................................................................................8 MICROPROCESSOR INTERFACE ...............................................................................................................9 LCD DRIVER OUTPUTS .............................................................................................................................11 TEST PINS..................................................................................................................................................11 FUNCTIONAL DESCRIPTION............................................................................................................................12 MICROPROCESSOR INTERFACE .............................................................................................................12 DISPLAY DATA RAM (DDRAM) ..................................................................................................................16 LCD DISPLAY CIRCUITS............................................................................................................................19 LCD DRIVER CIRCUIT ...............................................................................................................................21 POWER SUPPLY CIRCUITS ......................................................................................................................22 REFERECE CIRCUIT EXAMPLES..............................................................................................................28 RESET CIRCUIT .........................................................................................................................................29 INSTRUCTION DESCRIPTION...........................................................................................................................30 SPECIFICATIONS..............................................................................................................................................43 ABSOLUTE MAXIMUM RATINGS...............................................................................................................43 DC CHARACTERISTICS.............................................................................................................................44 REFERENCE DATA....................................................................................................................................47 AC CHARACTERISTICS .............................................................................................................................49 REFERENCE APPLICATIONS...........................................................................................................................53 MICROPROCESSOR INTERFACE .............................................................................................................53 CONNECTIONS BETWEEN KS0715 AND LCD PANEL..............................................................................54 TCP PIN LAYOUT (SAMPLE)......................................................................................................................57
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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The KS0715 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 33 common and 100 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8bit parallel display data and stores in an on-chip display data RAM of 65 x 132 bits. It provides a highly-flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
Driver Output Circuits - - - - 33 common outputs / 100 segment outputs On-chip Display Data RAM Capacity: 65 x 132 = 8,580 bits Bit data "1": a dot of display is illuminated. Bit data "0": a dot of display is not illuminated.
Multi-chip Operation (Master, Slave) Available Applicable Duty Ratios Duty ratio 1/33 Microprocessor Interface - - 8-bit parallel bi-directional interface with 6800-series or 8080-series Serial interface (only write operation) available Applicable LCD bias 1/5 or 1/6 Maximum display area 33 x 100
Various Instruction Setting On-chip Low Power Analog Circuit - - - - - - - - - - - On-chip oscillator circuit Voltage converter (x2, x3 and x4) Voltage regulator (temperature coefficient: -0.05%/C, -0.2%/C) On-chip electronic contrast control function (32 steps) Voltage follower (LCD bias: 1/5 or 1/6)
Operating Voltage Range Supply voltage (VDD): 2.4 to 3.6 V LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V 100 Typ. (VDD = 3V, x4 boosting, V0 = 8V, internal power supply ON and display OFF) 10 Max. (during power save [standby] mode) Ta = -40C to +85C Gold bumped chip or TCP
Low Power Consumption
Wide Operating Temperature Range Package Type
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
Series Specifications Product code KS0715UM-L0CC KS0715UM-L4CC KS0715UM-H0CC KS0715UM-H4CC KS0715TB-XX-L0TF KS0715TB-XX-L4TF KS0715TB-XX-H0TF KS0715TB-XX-H4TF TEMPS pin 0 (VSS connected) 1 (VDD connected) 0 (VSS connected) 1 (VDD connected) Temp. coefficient -0.05%/C COG -0.2%/C Package Chip thickness 670 m 470 m 670 m 470 m 670 m -0.05%/C TCP -0.2%/C 470 m 670 m 470 m
* XX: TCP ordering number
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
BLOCK DIAGRAM
COM31
SEG98 : SEG66 SEG65 SEG64
SEG99
COMS
COMS
COM0
SEG0
SEG1
:
:
:
VDD V0 V1 V2 V3 V4 VSS
100 SEGMENT DRIVER CIRCUITS
34 COMMON DRIVER CIRCUITS
SEGMENT CONTROLLER V/F CIRCUIT PAGE I/O ADDRESS BUFFER CIRCUIT V/R CIRCUIT
COMMON CONTROLLER
V0 VR TEMPS
DISPLAY DATA RAM 65 X 132 = 8,580 Bits
LINE ADDRESS CIRCUIT
DISPLAY TIMING GENERATOR CIRCUIT
MS CL M FRS DISP
COLUMN ADDRESS CIRCUIT OSCILLATOR TESTL2
VOUT C1C1+ C2C2+ C3C3+
V/C CIRCUIT
TESTL1 STATUS REGISTER BUS HOLDER INSTRUCTION REGISTER INSTRUCTION DECODER
MPU INTERFACE (PARALLEL & SERIAL)
Figure 1. Block Diagram
DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCLK) DB7(SID) MI RESETB PS RW_WR E_RD RS CS2 CS1B
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
PAD CONFIGURATION
209 108
- - - - - - - - - -
Y (TOP VIEW)
- - - -
- - - -
210
107
KS0715
(0,0)
X
234
- - - - - - - - - -
1 82
83
Figure 2. KS0715 Chip Configuration
Table 1. KS0715 Pad Dimensions Item Chip size Pad pitch Pad No. 1 to 82 83 to 234 1 to 82 Bumped pad size 83 to 107 108 to 209 210 to 234 Bumped pad height COG Align Key Coordinate
30m 30m 30m 30m 30m 30m 30m 30m 30m
Size X 7980 90 70 56 108 50 108 17 (Typ.) ILB Align Key Coordinate
42m 108m
Y 2700
Unit
114 50 108 50 m
All pad
108m
42m
(-3870, +1230) 60m
(+3870, +1230)
42m
42m
(-3832, -1055)
30m
(+3832, -1070)
108m
108m
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates [Unit: m]
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Name
DUMMY TESTL1 VDD FRS M CL DISP VDD MS VSS RESETB VDD PS VSS CS1B CS2 VDD MI VSS VDD RS VSS RW_WR E_RD VDD VDD VDD VDD VDD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VSS VSS VSS VSS VSS VOUT VOUT C3+ C3+ C3C3-
X
-3645 -3555 -3465 -3375 -3285 -3195 -3105 -3015 -2925 -2835 -2745 -2655 -2565 -2475 -2385 -2295 -2205 -2115 -2025 -1935 -1845 -1755 -1665 -1575 -1485 -1395 -1305 -1215 -1125 -1035 -945 -855 -765 -675 -585 -495 -405 -315 -225 -135 -45 45 135 225 315 405 495 585 675 765
Y
-1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226
No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Name
C1+ C1+ C1C1C2+ C2+ C2C2VSS VSS VR VR V0 V0 V0 V0 V0 V0 V1 V1 V2 V2 V3 V3 V4 V4 VSS VSS TEMPS VDD TESTL2 DUMMY DUMMY DUMMY DUMMY DUMMY COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2
X
855 945 1035 1125 1215 1305 1395 1485 1575 1665 1755 1845 1935 2025 2115 2205 2295 2385 2475 2565 2655 2745 2835 2925 3015 3105 3195 3285 3375 3465 3555 3645 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830 3830
Y
-1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -1226 -840 -770 -700 -630 -560 -490 -420 -350 -280 -210 -140 -70 0 70 140 210 280 350
No.
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Name
COM1 COM0 COMS DUMMY DUMMY DUMMY DUMMY DUMMY SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41
X
3830 3830 3830 3830 3830 3830 3830 3535 3465 3395 3325 3255 3185 3115 3045 2975 2905 2835 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595
Y
420 490 560 630 700 770 840 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
Table 2. Pad Center Coordinates (Continued) [Unit: m]
No.
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Name
SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91
X
525 455 385 315 245 175 105 35 -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905
Y
1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190 1190
No.
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234
Name
SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 DUMMY DUMMY DUMMY DUMMY DUMMY COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COMS DUMMY DUMMY DUMMY DUMMY
X
-2975 -3045 -3115 -3185 -3255 -3325 -3395 -3465 -3535 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830 -3830
Y
1190 1190 1190 1190 1190 1190 1190 1190 1190 840 770 700 630 560 490 420 350 280 210 140 70 0 -70 -140 -210 -280 -350 -420 -490 -560 -630 -700 -770 -840
No.
Name
X
Y
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pin Description Name VDD VSS I/O Supply Supply Power supply Ground LCD driver supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier for application. Voltages should have the following relationship; V0 V1 V2 V3 V4 VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD Bias. LCD bias V1 V2 V3 V4 1/6 bias 1/5 bias (5/6) x V0 (4/5) x V0 (4/6) x V0 (3/5) x V0 (2/6) x V0 (2/5) x V0 (1/6) x V0 (1/5) x V0 Description
V0 V1 V2 V3 V4 I/O
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pin Description Name C1C1+ C2C2+ C3C3+ VOUT VR I/O O O O O O O I/O I Description Capacitor 1 negative connection pin for voltage converter Capacitor 1 positive connection pin for voltage converter Capacitor 2 negative connection pin for voltage converter Capacitor 2 positive connection pin for voltage converter Capacitor 3 negative connection pin for voltage converter Capacitor 3 positive connection pin for voltage converter Voltage converter input / output pin V0 voltage adjustment pin
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
SYSTEM CONTROL
Table 5. System Control Pin Description Name I/O Description Master / Slave operation select pin - MS = "H": master operation - MS = "L": slave operation The following table depends on the MS status. MS I MS H L OSC circuit Enabled Disabled Power supply circuit Input Disabled CL Output Input M Output Input FRS Output Output DISP Output Input
CL
I/O
Display clock input / output pin When the KS0715 is used in master/slave mode (multi-chip), the CL pins must be connected each other for sync. LCD AC signal input / output pin When the KS0715 is used in master/slave mode (multi-chip), the M pins must be connected each other. - MS = "H": output - MS = "L": input Static driver segment output pin This pin is used together with the M pin. LCD display blanking control input/output. When KS0715 is used in master/slave mode (multi-chip), the DISP pins must be connected each other. - MS = "H": output - MS = "L": input Selects temperature coefficient of the reference voltage - TEMPS = "L": -0.05%/C - TEMPS = "H": -0.2%/C
M
I/O
FRS
O
DISP
I/O
TEMPS
I
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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
MICROPROCESSOR INTERFACE
Table 6. Microprocessor Interface Pin Description Name RESETB I/O I Description Reset input pin When RESETB is "L", initialization is executed. Parallel / serial data input select input PS PS I H L Interface mode Parallel Serial Chip select CS1B, CS2 CS1B, CS2 Data / instruction RS RS Data DB0 to DB7 SID (DB7) Read / write E_RD RW_WR Write only Serial clock SCLK (DB6)
*NOTE: When PS is "L", DB0 to DB5 are high impedance and E_RD and RW_WR should be fixed to either "H" or "L". MI CS1B CS2 RS I Microprocessor interface select input pin - MI = "H": 6800-series MPU interface - MI = "L": 8080-series MPU interface Chip select input pins Data / instruction I/O is enabled only when CS1B is "L" and CS2 is "H". When chip select is non-active, DB0 to DB7 may be high impedance. Register select input pin - RS = "H": DB0 to DB7 are display data. - RS = "L": DB0 to DB7 are control data. Read / Write execution control pin MI H RW_WR I L 8080-series /WR MPU type 6800-series RW_WR RW Description Read/Write control input pin - RW = "H": read - RW = "L": write Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal.
I
I
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
Table 6. Microprocessor Interface Pin Description (Continued) Name I/O Read / Write execution control pin MI MPU Type E_RD Description Read / Write control input pin - RW = "H": When E is "H", DB0 to DB7 are in an output status. - RW = "L": The data on DB0 to DB7 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is "L", DB0 to DB7 are in an output status. Description
E_RD
I
H
6800-series
E
L
8080-series
/RD
DB0 to DB7
I/O
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS = "L"); - DB0 to DB5: high impedance - DB6: serial input clock (SCLK) - DB7: serial input data (SID) When chip select is not active, DB0 to DB7 may be high impedance.
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER OUTPUTS
Table 8. LCD Driver Outputs Pin Description Name I/O Description LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Display data SEG0 to SEG99 H O H L L Power save mode M H L H L Segment driver output voltage Normal display V0 VSS V2 V3 VSS Reverse display V2 V3 V0 VSS VSS
LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data COM0 to COM31 H O H L L Power save mode M H L H L Common driver output voltage VSS V0 V1 V4 VSS
COMS
O
Common output for the icons The output signals of two pins are same. When not used, these pins should be left open. In multi-chip (master/slave) mode, all COMS pins on both master and slave units are the same signal.
TEST PINS
Table 8. Test Pin Description Name TESTL1 TESTL2 I/O I IC test pins with pull-up These pins must be open. Description
NOTE: DUMMY - These pins should be opened (floated).
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input There are CS1B and CS2 pins for Chip Selection. The KS0715 can interface with an MPU only when CS1B is "L" and CS2 is "H". When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface KS0715 has three types of interface with an MPU, which are one serial and two parallel interface. This parallel or serial interface is determined by PS pin as shown in table 9. Table 9. Parallel / Serial Interface Mode PS H L Type Parallel Serial CS1B CS1B CS1B CS2 CS2 CS2 MI H L *x Interface mode 6800-series MPU mode 8080-series MPU mode Serial-mode
*x: Don't care
Parallel Interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in table 10. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 11. Table 10. Microprocessor Selection for Parallel Interface MI H L CS1B CS1B CS1B CS2 CS2 CS2 RS RS RS E_RD E /RD RW_WR RW /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series
Table 11. Parallel Data Transfer Common RS H H L L 6800-series E_RD (E) H H H H RW_WR (RW) H L H L 8080-series E_RD (/RD) L H L H RW_WR (/WR) H L H L Description Display data read out Display data write Register status read Writes to internal register (instruction)
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Serial interface (PS = "L") When the KS0715 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended.
CS1B
CS2
SID
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
SCLK
RS
Figure 3. Serial Interface Timing Busy Flag The Busy Flag indicates whether the KS0715 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
Data Transfer The KS0715 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
MPU signals
RS
/WR
DB0 to DB7
N
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
/WR N D(N) D(N+1) D(N+2) D(N+3)
BUS HOLDER
COLUMN ADDRESS
N
N+1
N+2
N+3
Figure 4. Write Timing
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
MPU signals
RS /WR /RD DB0 to DB7 N Dummy D(N) D(N+1)
Internal signals
/WR /RD BUS HOLDER COLUMN ADDRESS N N D(N) N+1 D(N+1) N+2 D(N+2) N+3
Figure 5. Read Timing
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
DB0 DB1 DB2 DB3 DB4
0 1 0 1 0
0 0 1 0 0
1 0 1 1 0
------
0 1 0 0 1
COM0 COM1 COM2 COM3 COM4 LCD Display
------
Display Data RAM
Figure 6. RAM-to-LCD Data Transfer Page Address Circuit
This circuit is for providing a page address to Display Data RAM shown in figure 8. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 8 (DB3 is "H", but DB2, DB1 and DB0 are "L") is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on-chip RAM. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the 132-bit RAM data to the 100 display data latch circuit. However, display data of icons are not scrolled because the MPU can not access Line Address of icons.
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Column Address Circuit Column Address circuit has an 8-bit preset counter that provides column address to the Display Data RAM as shown in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this address is increased by 1 each a read or write Data instruction, microprocessor can access the display data continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the column address counter is independent of page address register. ADC select instruction makes it possible to invert the relationship between the column address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the following figure 7. SEG output Column address [Y7:Y0] Display data LCD panel display ( ADC = 0 ) 00H~ 0FH x Not outputted SEG 0 10H 1 SEG 1 01H 0 SEG 2 02H 0 ... ... ... ... ... ... SEG 97 71H 0 SEG 98 72H 1 SEG 99 73H 1 74H~ 83H 0 Not outputted
LCD panel display ( ADC = 1 )
Not outputted
... ...
Not outputted
Figure 7. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
Page Address
DB3 DB2 DB1 DB0
Data
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 00 83 0F 10 11 12 74 73 72 71 SEG0 SEG1 SEG2 -
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COMS
0
0
0
0
Page0
0
0
0
1
Page1
0
0
1
0
Page2
0
0
1
1
Page3
Start
0
1
0
0
Page4
0
1
0
1
Page5
0
1
1
0
Page6
0
1
1
1
Page7
1
0
Column Address
0
0
Page8
ADC=0 ADC=1
-------------
71 72 73 74 12 11 10 1F SEG97 SEG98 SEG99 -
-
83 00 -
Initial start line address = 1CH
LCD Output
Figure 8. Display Data RAM Map
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DISPLAY CIRCUITS
Oscillator This is completely on-chip Oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. * Test Condition: Temperature: 25C & 85C, TEMPS = "L", No Load
VDD vs. fosc 4.00 3.50 3.00 2.50 fosc 2.00 [kHz] 1.50 1.00 0.50 0.00 2.4 2.7 3.0 3.3 3.6 VDD [V] 4.0 4.5 5.0 5.5 1/33 Duty (25C) 1/33 Duty (85C)
Figure 9. VDD vs. fOSC Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock (CL) and the 100-bit display data is latched by the display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and internal timing signal are shown in figure 10. In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 12 shows the M, CL, and DISP status. Table 12. Master and Slave Timing Signal Status Operation mode Master Slave Oscillator ON (internal clock used) OFF (external clock used) M Output Output Input CL Output Input Input DISP Output Output Input
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32
33
1
2
3
4
5
6
7
8
9
10
11
12
26
27
28
29
30
31
32
33
1
2
3
4
5
6
CL
M
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 9. 2-frame AC Driving Waveform Common Output Control Circuit This circuit controls the relationship between the number of common output and specified duty ratio. SHL Select Instruction specifies the scanning direction of the common output pins. Table 13. The Relationship between Duty Ratio and Common Output Duty SHL 0 1/33 1 COM31 to COM0 Common output pins COM0 to COM31 COM0 to COM31 COMS COMS
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER CIRCUIT
This driver circuit is configured by 34-channel (including 2 COMS channel) common driver and 100-channel segment driver. This LCD panel driver voltage depends on the combination of display data and M signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
VDD
M
VSS V0 V1 V2
COM0
V3 V4 VSS V0 V1 V2
COM1
V3 V4 VSS V0 V1 V2
COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
COM2
V3 V4 VSS V0 V1 V2
SEG0
V3 V4 VSS V0 V1 V2
SEG1
V3 V4 VSS V0 V1 V2
SEG2
V3 V4 VSS
Figure 10. Segment and Common Timing
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KS0715
POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with lowpower consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For details, refers to "Instruction Description". Table 14 shows the referenced combinations in using Power Supply circuits. Table 14. Recommended Power Supply Combinations User setup Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power control (VC VR VF) 111 V/C circuits ON V/R circuits ON V/F circuits ON VOUT V0 V1 to V4
Open
Open
Open
011
OFF
ON
ON
External input
Open
Open
001 000
OFF OFF
OFF OFF
ON OFF
Open Open
External input External input
Open External input
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Voltage Converter Circuits These circuits boost up the electric potential between VDD and VSS to 2, 3, or 4 times toward positive side and boosted voltage is outputted from VOUT pin. [C1 = 1.0 to 4.7 F]
VDD VDD VOUT C3+ C3 C2+ C2 C1+ C1 + C1 VDD VDD VOUT C3+ C3 C2+ C2 C1+ C1 +
C1
+ -
VOUT = 2 x VDD C1 VDD VSS
VOUT = 3 x VDD + C1 + C1 VDD VSS
VSS GND
VSS GND
Figure 11. Two Times Boosting Circuit
Figure 12. Three Times Boosting Circuit
V DD V DD VOUT C3+ C3 C2+ C2 C1+ C1 + + C1 C1 VOUT = 4 x V DD
+ C1 + C1 -
V DD V SS
V SS GND
Figure 13. Four Times Boosting Circuit
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Voltage Regulator Circuits The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 14, it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 31. VREF voltage at Ta = 25C is shown in table 15-1. Rb V0 = ( 1 + ) x VEV [V] ------ (Eq. 1) Ra (31 - ) VEV = ( 1 - ) x VREF [V] ------ (Eq. 2) 150 Table 15-1. VREF Voltage at Ta = 25C TEMPS L H Temp. coefficient -0.05% / C -0.2% / C Table 15-2. Reference Voltage Parameter () SV4 0 0 : : 1 1 SV3 0 0 : : 1 1 SV2 0 0 : : 1 1 SV1 0 0 : : 1 1 SV0 0 1 : : 0 1 Reference voltage parameter () 0 1 : : 30 31 VREF [V] 1.9 2.1
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
VOUT
+ V EV -
V0 Rb VR
Ra V SS
GND
Figure 14. Internal Voltage Regulator Circuit
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In Case of Using External Resistors, Ra and Rb It is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 8V 2. 5-bit reference voltage register = (1, 1, 1, 1, 1) 3. Maximum current flowing Ra, Rb = 1 uA From Eq. 1 Rb 8 = ( 1 + ) x VEV [V] ------ (Eq. 3) Ra From Eq. 2 (31 - 31) VEV = ( 1 - ) x 1.9 = 1.9 [V] ------ (Eq. 4) 150 From requirement 3. 8 = 1 [uA] ------ (Eq. 5) Ra + Rb
From equations Eq. 3, 4 and 5 Ra = 1.9 [M] Rb = 6.1 [M] The following table shows the range of V0 depending on the above requirements. Table 16. V0 depending on Electronic Volume Level Electronic volume level 0 V0 6.33 ....... ....... 16 7.19 ....... ....... 31 8
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Voltage Follower Circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance are converted by the Voltage Follower for increasing drive capability. Table 17 shows the relationship between V1 to V4 level and bias. Table 17. The Relationship between V1 to V4 Level and Bias Duty ratio 1/33 LCD bias 1/6 1/5 V1 (5/6) x V0 (4/5) x V0 V2 (4/6) x V0 (3/5) x V0 V3 (2/6) x V0 (2/5) x V0 V4 (1/6) x V0 (1/5) x V0
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REFERECE CIRCUIT EXAMPLES
VDD C1 C1 C1 C1 Ra C2 C2 C2 C2 C2 VSS + + + + + Rb V0 V1 V2 V3 V4 MS VOUT C3+ C3C2+ C2C1+ C1VR
VDD MS External Power Supply VOUT C3+ C3C2+ C2C1+ C1VR + + + + + Rb V0 V1 V2 V3 V4
Ra C2 C2 C2 C2 C2 VSS -
Figure 15. When Using all LCD Power Circuits (4-time V/C: ON, V/R: ON, V/F: ON)
Figure 16. When not Using V/C Circuit
VDD MS VOUT C3+ C3C2+ C2C1+ C1VR C2 C2 C2 C2 C2 VSS + + + + + V0 V1 V2 V3 V4
VDD MS VOUT C3+ C3C2+ C2C1+ C1VR External Power Supply V0 V1 V2 V3 V4
Value of external Capacitance Item C1 C2 Value 1.0 to 4.7 0.47 to 1.0 Unit F
External Power Supply
VSS
Figure 17. When Using some LCD Power Circuits (V/C: OFF, V/R: OFF, V/F: ON)
Figure 18. When not Using Internal LCD Power Supply Circuit
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
RESET CIRCUIT
Setting RESETB to "L" or Reset instruction can initialize internal function. When RESETB becomes "L", following procedure is occurred. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) LCD bias ratio: 1/6 Read-modify-write: OFF SHL select: OFF (normal) Static indicator mode: OFF Display start line: 0 (first) Column address: 0 Page address: 0 Reference voltage set: off Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0) When RESET instruction is issued, following procedure is occurred. Read-modify-write: OFF Static indicator mode: OFF SHL select: 0 Display start line: 0 (first) Column address: 0 Page address: 0 Reference voltage set: OFF Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0)
While RESETB is "L" or reset instruction is executed, no instruction except read status could be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
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INSTRUCTION DESCRIPTION
Table 18. Instruction Table Instruction
Read display data Write display data Read status Display ON / OFF Initial display line Set reference voltage mode Set reference voltage register Set page address Set column address MSB Set column address LSB
RS 1 1 0 0 0 0 0 0 0 0
RW 1 0 1 0 0 0 0 0 0 0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
x : Don't care Description
Read data from DDRAM Write data into DDRAM
Read data Write data BUSY 1 0 1 1 1 0 0 ADC 0 1 0 0 0 0 0 ON/OFF 1 ST5 0 0 1 0 0 RESETB 0 ST4 0 SV4 1 1 0 0 1 ST3 0 SV3 P3 0 Y3 0 1 ST2 0 SV2 P2 Y6 Y2 0 1 ST1 0 SV1 P1 Y5 Y1 0 DON ST0 1 SV0 P0 Y4 Y0
Read the internal status Turn ON / OFF LCD panel When DON = 0: display OFF When DON = 1: display ON Specify DDRAM line for COM0 Set reference voltage mode Set reference voltage register Set page address Set column address MSB Set column address LSB Select SEG output direction When ADC = 0: normal direction (SEG0SEG99) When ADC = 1: reverse direction (SEG99SEG0) Select normal / reverse display When REV = 0: normal display When REV = 1: reverse display Select normal/ entire display ON When EON = 0: normal display. When EON = 1: entire display ON Select LCD bias Set modify-read mode release modify-read mode Initialize the internal functions Select COM output direction When SHL = 0: normal direction (COM0COM31) When SHL = 1: reverse direction (COM31COM0) Control power circuit operation Set static indicator register SI = 0 (OFF), SI = 1 (ON) Compound instruction of display OFF and entire display ON Don't use this instruction.
ADC select
0
0
1
0
1
0
0
0
0
ADC
Reverse display ON / OFF
0
0
1
0
1
0
0
1
1
REV
Entire display ON / OFF LCD bias select Set modify-read Reset modify-read Reset
0 0 0 0 0
0 0 0 0 0
1 1 1 1 1
0 0 1 1 1
1 1 1 1 1
0 0 0 0 0
0 0 0 1 0
1 0 0 1 0
0 1 0 1 1
EON BIAS 0 0 0
SHL select
0
0
1
1
0
0
SHL
x
x
x
Power control Set static indicator register Power save Test instruction
0 0 0
0 0 0
0 1 1
0 0 1
1 1 1
0 0 1
1 1 x
VC 1 x
VR 0 x
VF SI x
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Read Display Data 8-bit data from Display Data RAM specified by the column address and page address could be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS 1 Write Display Data 8-bit data of display data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS 1 RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RW 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Read data
Write data
Set Page Address Set Column Address Data Write Column = Column + 1 YES
Set Page Address Set Column Address Dummy Data Read Column = Column + 1 Data Read Column = Column + 1 YES
Data Write Continue ? NO Optional Status
Data Read Continue ? NO Optional Status
Figure 19. Sequence for Writing Display Data
Figure 20. Sequence for Reading Display Data
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Read Status Indicates the internal status of the KS0715 RS 0 RW 1 DB7 BUSY DB6 ADC DB5 ON / OFF DB4 RESETB DB3 0 DB2 0 DB1 0 DB0 0
Flag BUSY
Description The device is busy when internal operation or reset Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG99 SEG0), 1: normal direction (SEG0 SEG99) Indicates display ON / OFF status 0: display ON, 1: display OFF Indicates the initialization is in progress by RESETB signal 0: chip is active, 1: chip is being reset
ADC ON / OFF RESETB Display ON / OFF
Turns the display ON or OFF RS RW DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 DON
0 0 DON = 1: display ON DON = 0: display OFF Initial Display Line
Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed at the top row (COM0 when SHL = L, COM31 when SHL = H) of LCD panel. RS 0 ST5 0 0 : 1 1 RW 0 ST4 0 0 : 1 1 DB7 0 ST3 0 0 : 1 1 DB6 1 ST2 0 0 : 1 1 DB5 ST5 ST1 0 0 : 1 1 DB4 ST4 ST0 0 1 : 0 1 DB3 ST3 DB2 ST2 DB1 ST1 DB0 ST0
Line address 0 1 : 62 63
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Reference Voltage Select Consists of 2-byte Instruction The 1st instruction sets reference voltage mode, the 2nd one updates the contents of reference voltage register. After second instruction, reference voltage mode is released. The 1st Instruction: Set Reference Voltage Select Mode RS RW DB7 DB6 DB5 DB4 0 0 1 0 0 0
DB3 0
DB2 0
DB1 0
DB0 1
The 2nd Instruction: Set Reference Voltage Register RS RW DB7 DB6 DB5 0 SV4 0 0 : : 1 1 0 SV3 0 0 : : 1 1 1 SV2 0 0 : : 1 1 0 SV1 0 0 : : 1 1 0 SV0 0 1 : : 0 1
DB4 SV4
DB3 SV3
DB2 SV2
DB1 SV1
DB0 SV0
Reference voltage parameter () 0 1 : : 30 31
Setting Reference Voltage Start 1st Instruction for Mode Setting 2nd Instruction for Register Setting Setting Reference Voltage End
Figure 21. Sequence for Setting the Reference Voltage
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Set Page Address Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the Page Address doesn't effect to the display status. RS 0 P3 0 0 : 0 1 RW 0 P2 0 0 : 1 0 DB7 1 P1 0 0 : 1 0 DB6 0 P0 0 1 : 1 0 DB5 1 DB4 1 DB3 P3 Page 0 1 : 7 8 DB2 P2 DB1 P1 DB0 P0
Set Column Address Sets the Column Address of display RAM from the microprocessor into the column address register. Along with the Column Address, the Column Address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically increased. Set Column Address MSB RS RW DB7 0 0 0
DB6 0
DB5 0
DB4 1
DB3 0
DB2 Y6
DB1 Y5
DB0 Y4
Set Column Address LSB RS RW DB7 0 Y6 0 0 : 1 1 0 Y5 0 0 : 1 1 0 Y4 0 0 : 0 0
DB6 0 Y3 0 0 : 0 0
DB5 0 Y2 0 0 : 0 0
DB4 0 Y1 0 0 : 1 1
DB3 Y3 Y0 0 1 : 0 1
DB2 Y2
DB1 Y1
DB0 Y0
Column address 0 1 : 98 99
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
ADC Select Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins could be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC
0 0 1 0 ADC = 0: normal direction (SEG0 SEG99) ADC = 1: reverse direction (SEG99 SEG0) Reverse Display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS 0 REV 0 (normal) 1 (reverse) Reverse Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF instruction. RS RW DB7 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV
RAM bit data = "1" LCD pixel is illuminated LCD pixel is not illuminated
RAM bit data = "0" LCD pixel is not illuminated LCD pixel is illuminated
0 0 1 EON = 0: normal display EON = 1: entire display ON Select LCD Bias
Selects LCD bias ratio of the voltage required for driving the LCD. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 LCD bias Bias = 0 1/6 Bias = 1 1/5 DB3 0 DB2 0 DB1 1 DB0 Bias
Duty ratio 1/33
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Set Modify-read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. RS 0 Reset Modify-read This instruction cancels the Modify-read mode, and makes the column address return to its initial value just before the set Modify-read instruction is started. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Set Page Address Set Column Address (N) Set Modify-Read Dummy Read Data Read Data Process Data Write NO
Change Complete ? YES Reset Modify-Read Return Column Address (N)
Figure 22. Sequence for Cursor Display
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Reset This instruction Resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESETB pin. RS 0 SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS 0 RW 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x x : Don't care RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
SHL = 0: normal direction (COM0 COM31) SHL = 1: reverse direction (COM31 COM0) Power Control
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS 0 VC 0 1 0 1 0 1 Set Static Indicator State This instruction sets the Static Indicator ON / OFF. When it is on, the static indicator operates and blinks at an interval of approximately 1second. Set Static Indicator Register RS 0 SI 0 1 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 0 DB0 SI RW 0 VR DB7 0 VF DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF
Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
Status of static indicator output OFF ON (about 1 second blinking)
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KS0715
Power Save (Compound Instruction) If the entire display ON / OFF instruction is issued during the display OFF state, KS0715 enters the Power Save status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, Power Save is entered to one of two modes (sleep and standby mode). When static indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released by the display ON & entire display OFF instruction.
Static Indicator OFF
Static Indicator ON
Power Save (Compound Instruction) [Display OFF] [Entire Display ON]
Sleep Mode [Oscillator Circuit: OFF] [LCD Power Supply Circuit: OFF] [All COM / SEG Outputs: VSS] [Consumption Current: < 2A]
Standby Mode [Oscillator Circuit: ON] [LCD Power Supply Circuit: OFF] [All COM / SEG Outputs: VSS] [Consumption Current: < 10A]
Power Save OFF (Compound Instruction) [Entire Display OFF] [Static Indicator ON] [Display ON]
Power Save OFF (Compound Instruction) [Entire Display OFF] [Display ON]
Release Sleep Mode
Release Standby Mode
Figure 23. Power Save Routine
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (1)
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB Pin = "H"
User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select]
User LCD Power Setup by Internal Instructions [Reference Voltage Register Set]
User LCD Power Setup by Internal Instructions [Voltage Converter ON] Waiting for 1ms User LCD Power Setup by Internal Instructions [Voltage Regulator ON] Waiting for 1ms User LCD Power Setup by Internal Instructions [Voltage Follower ON]
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 24. Initializing with the Built-in Power Supply Circuits
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Referential Instruction Setup Flow (2)
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB Pin = "H"
Set Power Save
User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select]
User LCD Power Setup by Internal Instructions [Reference Voltage Register Set]
Release Power Save
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 25. Initializing without the Built-in Power Supply Circuits
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (3)
End of Initialization
Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Display ON / OFF by Instruction [Display ON / OFF]
Turn Display ON / OFF by Instruction [Display ON / OFF]
End of Data Display
Figure 26. Data Displaying
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Referential Instruction Setup Flow (4)
Optional Status
Turn Display ON / OFF by Instruction [Display OFF]
User LCD Power Setup by Internal Instructions [Voltage Regulator OFF] Waiting for 50ms User LCD Power Setup by Internal Instructions [Voltage Follower OFF] Waiting for 1ms User LCD Power Setup by Internal Instructions [Voltage Converter OFF] Waiting for 1ms Power OFF (VDD-VSS)
Figure 27. Power OFF
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 19. Absolute Maximum Ratings Parameter Supply voltage range Input voltage range Operating temperature range Storage temperature range
NOTES: 1. VDD and VLCD are based on VSS = 0V. 2. Voltages V0 V1 V2 V3 V4 VSS must always be satisfied. (VLCD = V0 - VSS) 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
Symbol VDD VLCD VIN TOPR TSTR
Rating - 0.3 to +7.0 - 0.3 to +17.0 - 0.3 to VDD +0.3 - 40 to +85 - 55 to +125
Unit V V V C C
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KS0715
DC CHARACTERISTICS
Table 20. DC Characteristics ( VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85C ) Item Operating voltage (1) Operating voltage (2) High Input voltage Low Output voltage High Low VIL VOH VOL IIL IOZ RON fOSC fCL IOH = -0.5mA IOL = 0.5mA VIN = VDD or VSS VIN = VDD or VSS Ta = 25C, V0 = 8V Ta = 25C x2 Voltage converter input voltage VDD x3 x4 Voltage converter output voltage Voltage regulator operating voltage Voltage follower operating voltage Reference voltage VOUT x2 / x3 / x4 voltage conversion (no-load ) VSS 0.8VDD VSS - 1.0 - 3.0 17 2.13 2.4 2.4 2.4 95 2.0 22.5 2.81 99 0.2VDD VDD V 0.2VDD + 1.0 + 3.0 3.0 27 3.37 3.6 3.6 3.6 % VOUT V VDD A A k kHz *5 *6 SEGn COMn *7 CL *8 *4 Symbol VDD V0 VIH Condition Min. 2.4 4.0 0.8VDD Typ. Max. 3.6 15.0 VDD V *3 Unit V V Pin used VDD *1 V0 *2
Input leakage current Output leakage current LCD driver ON resistance Oscillator frequency (1) Internal External
VOUT V0 VREF0 VREF1 Ta = 25C -0.05%/C -0.2%/C
4.0 4.0 1.84 2.04
1.9 2.1
15.0 15.0 1.96 2.16
V V V V
VOUT V0 *9 *10 *10
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Dynamic Current Consumption (1): when the Built-in Power Circuit is OFF (At Operate Mode) (Ta = 25C) Item Dynamic current consumption (1) Symbol IDD1 Condition VDD = 3.0V V0 - VSS = 8.0V Display OFF, checker pattern Min. Typ. 5 Max. 20 Unit Pin used *11
Dynamic Current Consumption (2): when the built-in power circuit is ON (At operate mode) Item Symbol Condition VDD = 3.0V, quad boosting, V0 - VSS = 8.0V, 1/65 duty ratio, Display OFF, checker pattern Normal power mode VDD = 3.0V, quad boosting, V0 - VSS = 8.0V, Display ON, checker pattern Normal power mode Min. Typ. Max. Unit (Ta = 25C) Pin used
-
47
70
Dynamic current consumption (2)
IDD2
*12
-
75
100
Current Consumption during Power Save mode (Ta = 25C) Item Sleep mode Standby mode Symbol IDDS1 IDDS2 Condition During sleep During standby Min. Typ. Max. 2.0 10.0 Unit A A Pin used
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
Table 21. The relationship between oscillation frequency and frame frequency Duty ratio Item On-chip oscillator circuit is used 1/33 On-chip oscillator circuit is not used fCL fOSC
fM fOSC 16 x 33 fOSC

8 External input (fCL)
2 x 33 (fOSC: oscillation frequency, fCL: display clock frequency, fM: LCD AC signal frequency)
[* Remark Solves] *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2. In case of external power supply is applied. *3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins. *4. DB0 to DB7, M, FRS, DISP, CL pins. *5. CS1B, CS2, RS, DB[7:0], E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins. *6. Applies when the DB[7:0], M, DISP, and CL pins are in high impedance. *7. Resistance value when 0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON= V / 0.1 [k] (V: voltage change when 0.1[mA] is applied in the ON status.) *8. See table 21 for the relationship between oscillation frequency and frame frequency. *9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range. *10. On-chip reference voltage source of the voltage regulator circuit to adjust V0. *11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc.
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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
REFERENCE DATA
IDD1 vs. VDD l Test Condition: Temperature (25C & 85C), V0 = 8V (External), TEMPS = 'L', 1/33 Duty, Ra = 1 [M], Rb = 3 [M], Normal Power Mode
VDD vs. IDD1(Pattern OFF) 12.00 10.00 8.00 IDD1 6.00 [uA] 4.00 2.00 0.00 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 VDD [V] Figure 28. Display Pattern is OFF 8.0V, 1/33 Duty (25C) 8.0V, 1/33 Duty (85C)
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
IDD2 vs. VDD l Test Condition: Temperature (25C & 85C), Quad boosting, RR = 6, EV = 32, TEMPS = 'L', 1/33 duty, Ra = 1 [M], Rb = 3 [M], Normal Power Mode
VDD vs. IDD2 (Pattern OFF) 50.00 45.00 40.00 35.00 30.00 IDD2 25.00 [uA] 20.00 15.00 10.00 5.00 0.00 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 VDD [V]
1/33 Duty (25C) 1/33 Duty (85C)
Figure 29. Display Pattern is OFF
VDD vs. IDD2 (Checker Pattern) 250.00 200.00 IDD2 [uA] 150.00 100.00 50.00 0.00 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 VDD [V] 1/33 Duty (25C) 1/33 Duty (85C)
Figure 30. Display Pattern is Checker
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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
AC CHARACTERISTICS
Read / Write Characteristics (8080-series MPU)
RS tAS80 CS1B (CS2 = 1) tPW80(R), RD, WR 0.9VDD 0.1VDD tDS80 DB0 to DB7 (Write) tACC80 DB6 to DB7 (Read) tOD80 tDH80 tPW80(W) tAH80
tCY80
Figure 31. Read / Write Characteristics (8080-series MPU) (VDD = 2.4 to 3.6V, Ta = -40 to +85C) Typ. Max. Unit Remark 125 90 ns ns ns ns ns ns CL = 100 pF
Item Address setup time Address hold time System cycle time Pulse width (WR) Pulse width (RD) Data setup time Data hold time Read access time Output disable time
Signal RS RS RW_WR E_RD DB7 to DB0
Symbol tAS80 tAH80 tCY80 tPW80(W) tPW80(R) tDS80 tDH80 tACC80 tOD80
Min. 13 17 400 55 125 35 13 10
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
Read / Write Characteristics (6800-series Microprocessor)
RS tAS68 CS1B (CS2 = 1) tPW68(R), tPW68(W) E 0.1VDD 0.9VDD tDS68 DB0 to DB7 (Write) tACC68 DB0 to DB7 (Read) tOD68 tDH68 tAH68
tCY68
Figure 32. Read / Write Characteristics (6800-series Microprocessor) (VDD = 2.4 to 3.6V, Ta = -40 to +85C) Max. Unit Remark 125 90 ns ns ns ns CL = 100 pF
Item Address setup time Address hold time System cycle time Data setup time Data hold time Access time Output disable time Enable pulse Read width Write
Signal RS RS DB7 to DB0 E_RD
Symbol tAS68 tAH68 tCY68 tDS68 tDH68 tACC68 tOD68 tPW68(R) tPW68(W)
Min. 13 17 400 35 13 10 125 55
Typ. -
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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Serial Interface Characteristics
tCSS CS1B (CS2 = 1) RS tCYS DB6 (SCLK) 0.9VDD 0.1VDD tWLS tDSS DB7 (SID) tASS
tCHS tAHS
tWHS tDHS
Figure 33. Serial Interface Characteristics (VDD = 2.4 to 3.6V, Ta = -40 to +85C ) Max Unit Remark ns
Item Serial clock cycle SCLK high pulse width SCLK low pulse width Address setup time Address hold time Data setup time Data hold time CS1B setup time CS1B hold time
Signal DB6 (SCLK) RS DB7 (SID) CS1B
Symbol tCYS tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS
Min 450 180 135 90 360 90 90 55 180
Typ -
ns ns ns
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
Reset Input Timing
tRW RESETB
Figure 34. Reset Input Timing (VDD = 2.4 to 3.6V, Ta = -40 to +85C) Typ. Remark Max. Unit ns
Item Reset low pulse width
Signal RESETB
Symbol tRW
Min. 900
Display Control Output Timing
tDM CL M
Figure 35. Display Control Output Timing (VDD = 2.4 to 3.6V, Ta = -40 to +85C) Typ. Remark Max. Unit 13 70 ns
Item M delay time
Signal M
Symbol tDM
Min. -
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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
In Case of Interfacing with 6800-series (PS = "H", MI = "H")
CS1B CS2 RS
CS1B CS2 RS E_RD RW_WR DB0 to DB7 RESETB MI PS
6800-series MPU
E RW DB0 to DB7 RESETB VDD VDD
KS0715
Figure 36. Interfacing with 6800-series (PS = "H", MI = "H") In Case of Interfacing with 8080-series (PS = "H", MI = "L")
8080-series MPU
CS1B CS2 RS /RD /W R DB0 to DB7 RESETB VSS VDD
CS1B CS2 RS E_RD
KS0715
RW_WR DB0 to DB7 RESETB MI PS
Figure 37. Interfacing with 8080-series (PS = "H", MI = "L") In Case of Serial Interface (PS = "L", MI = "H/L")
MPU
CS1B CS2 RS SID SCLK RESETB OPEN V D D or VS S VSS
CS1B CS2 RS KS0715 DB7(SID) DB6(SCLK) RESETB DB0 to DB5 MI PS
Figure 38. Serial interface (PS = "L", MI = "H/L")
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
CONNECTIONS BETWEEN KS0715 AND LCD PANEL
Single Chip Configuration (1/33 Duty Configurations)
COMS COM31 : COM16
KS0715 (Bottom View)
...........
COM15 : COM0 COMS
COM15 : COM0 COMS
KS0715 (Top View)
............
COMS COM31 : COM16
SEG99
SEG0
SEG0
SEG99

(R)

(R)
32 x 100 pixels
(R)
32 x 100 pixels
(R)
Figure 39. SHL = 0, ADC = 1
Figure 40. SHL = 0, ADC = 0

(R)

(R)
32 x 100 pixels
(R)
32 x 100 pixels
(R)
SEG0
COMS COM0 : COM15
...........
SEG99
COM16 : COM31 COMS
SEG99
COM16 : COM31 COMS
...........
SEG0
COMS COM0 : COM15
KS0715 (Bottom View)
KS0715 (Top View)
Figure 41. SHL = 1, ADC = 0
Figure 42. SHL = 1, ADC = 1
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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
Multiple Chip Configuration 33COM (32COM + 1COMS) x 200SEG (100SEG x 2)
COMS COM31 : COM16
KS0715 ( Bottom View ) ( Master )
...................
COM15 : COM0 COMS
COMS COM31 : COM16
SEG99
SEG0
SEG99
KS0715 ( Bottom View ) ( Slave )
...................
COM15 : COM0 COMS
SEG0

(R)
32 x 200 pixels
(R)
Figure 43. SHL = 0, ADC = 1 Connect the following pins of two chips each other - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4

(R)
32 x 200 pixels
(R)
SEG0
COMS COM0 : COM15
...............
SEG99
COM16 : COM31 COMS
SEG0
COMS COM0 : COM15
...............
SEG99
COM16 : COM31 COMS
KS0715 ( Bottom View ) ( Master )
KS0715 ( Bottom View ) ( Slave )
Figure 44. SHL = 1, ADC = 0 Connect the following pins of two chips each other - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4
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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
KS0715
-
66COM (64COM + 2COMS) x 100SEG
COM15 : COM0 COMS
KS0715 ( Top View ) ( Master )
...................
COMS COM31 : COM16
SEG0
SEG99

(R)
64 x 100 pixels

(R)
SEG99
COM16 : COM31 COMS
...................
SEG0
COMS COM0 : COM15
KS0715 ( Top View ) ( Slave )
Figure 45. 66COM (64COM + 2COMS) x 100SEG Connect the following pins of two chips each other - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4 Common / Segment output direction select - Master chip: SHL = 0, ADC = 0 - Slave chip: SHL = 1, ADC = 1
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KS0715
33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
TCP PIN LAYOUT (SAMPLE)
FRS M CL DISP MS RESETB PS CS1B CS2 MI RS RW_WR E_RD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VOUT C3+ C3C1+ C1C2+ C2VSS VR V0 V1 V2 V3 V4 VSS TEMPS
COMS COM31 COM30 : : : COM26 COM25 COM24 : : : COM19 COM18 COM17 COM16 SEG99 SEG98 SEG97 SEG96 : : : : SEG66 SEG65 SEG64 SEG63 : : : : SEG3 SEG2 SEG1 SEG0 COMS COM0 COM1 : : : COM7 COM8 COM9 : : : COM13 COM14 COM15 COMS
KS0715
Figure 46. TCP Pin Layout
(TOP VIEW)
57

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